Design-for-test and test engineering professionals throughout the entire semiconductor industry are preparing for 2.5D- and 3D-SICs (Stacked Integrated Circuits) to become product reality, with recent product announcements from a number of leading semiconductor companies, foundries, and assembly houses as public testimonials. Consequently, after experiencing a successful launch in 2010, the second edition of the 3D-TEST Workshop (in full: “IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits”), grew by 30% in 2011 to 129 attendees. Like last year, the 3D-TEST Workshop was organized in conjunction with the IEEE International Test Conference (ITC), the world’s premier test conference, and took place on September 19-23 at the Disneyland Hotel in Anaheim, California. Guest Blogger, Erik Jan Marinissen, imec, is the founder and Program Chair of this young and popular workshop. Here is his report on this year’s event.
We received many high-quality submissions this year, so to accommodate them all, we cut the presentation slots down to 15 minutes. While tough on the speakers, this allowed many speaking opportunities and a broad, diverse coverage of the entire 3D-TEST field. We had 17 paper presentations in five sessions covering academic research, EDA, wafer probing, standardization, and applications. In addition to regular paper presentations, the workshop featured two invited talks (from Samsung Semiconductor and TechSearch International), two panel sessions (one with industrial executives, and one on wide-I/O DRAM stacking), three poster and demo sessions, and various social events including an evening reception in the beautiful Rose Garden of the Disneyland Hotel. The full program can be found at http://3dtest.tttc-events.org. All of this was made possible through the organizational support of a global team of seven dedicated volunteers, the technical support of a forty-member strong Program Committee, and financial support of eight Corporate Supporters (Advantest, Cadence Design Systems, Intellitech, Mentor Graphics, MicroProbe, Synopsys, SynTest, and Tokyo Electron).
Below, I will give a brief summary of the workshop’s program. If you attended the workshop yourself (which you should be able to prove by putting on your exclusive ‘3D-TEST Workshop’ branded polo shirt!) and want to add to this, please feel free to do so.
- The opening keynote was delivered by Hong Hao, Vice President at Samsung Semiconductor. Samsung is obviously a key player in 2.5D and 3D chip stacking, with semiconductor activities in memories, logic, and the foundry business. Dr. Hao came in from the smart mobile device market, which has shown a mind-boggling growth, enabled by the technological progress in 3D packaging. On the flip side, these packaging techniques also bring several, still unresolved electrical and mechanical test challenges.
- In the following invited talk, Jan Vardaman, President of TechSearch International, a market research firm, presented an overview of the 2.5D- and 3D-markets (“from PowerPoint to Real Engineering Work”), citing TSV wafer probing and testing as the single remaining unresolved equipment challenge.
- The early Friday morning session included four presentations on academic research work in the 3D test field. Two of them (from National Taiwan University with Duke University and Linköping University in Sweden) played on advanced test scheduling, with an objective to minimize test length while meeting thermal and power constraints.
- The second Friday session focused on EDA tool support for 3D-SICs. In this session Cadence, Mentor Graphics, Synopsys, and SynTest presented their approaches to design-for-test and test generation for 3D-SICs. These approaches were also explained in more detail in dedicated demo sessions. Cadence and Mentor focused especially on DfT in the form of die wrappers, as proposed in the IEEE P1838 Working Group, which allows for the transport of test data up and down through the die stack.
- The next session was on wafer probing. A major challenge in this community is to probe on fine-pitch micro-bumps. The short-term target is set by the JEDEC standard-under-definition for Wide-I/O DRAMs, which specifies micro-bumps at 40/50µm pitch. The approach by Cascade Microtech, as presented by CTO Eric Strid, is to scale down the probe tip size, pitch, and force of their membrane probe cards. Ben Eldridge, CTO of market leader FormFactor, presented a novel approach with metal nano-fiber contacts, named NanoPierce, which aims to provide socketed probe access to singulated dies with fine-pitch micro-bumps. Matthew Losey of Touchdown Technologies gave insight in the design choices that enabled them to develop a multi-layer MEMS probe card at 40µm pitch.
- Just before lunch, there were two presentations on standardization. Larry Smith of Sematech presented an overview of 3D standardization efforts in general and Sematech’s dashboard for that (http://wiki.sematech.org/3D-Standards). I, Erik Jan Marinissen, presented the IEEE P1838 Working Group which focuses on 3D-DfT (http://grouper.ieee.org/groups/3Dtest).
- After lunch, the floor was given to semiconductor companies that actually implement and use these technologies. Presentations came from Austria Microsystems, Qualcomm, ST Microelectronics, and TSMC. The focus of most of these talks was on defects observed in TSVs, while Amer Cassier of Qualcomm presented technical, logistic, and business challenges with respect to the test flow of 3D-SICs.
- The workshop was concluded by a lively panel on the test challenges and solutions related to DRAM stacking in general and JEDEC’s upcoming standard on wide-I/O DRAMs in particular. Panelists were Sandeep Goel (TSMC), Gary Fleeman (Advantest and member of JEDEC’s standardization committee), Marc Greenberg (Cadence memory controller division), Michael Laisne (Qualcomm), and Michael Ricchetti (AMD). The test community would perhaps have liked to see more DfT in the Wide-I/O DRAMs, but as that standardization train seems to have left its station, the ‘communis opinio’ was that the boundary scan provided in the standard allows workable solutions and is a great step forward from prior DRAMs without DfT at all.
Planning is already underway for the third edition of the 3D-TEST Workshop: November 8+9, 2012 in Anaheim, California, again co-located with ITC. If you are serious about 2.5D- or 3D-SICs, you should make this a ‘must-attend’ event! ~ EJM
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