MEMS and 3D IC integration: Synergies in the Supply Chain

Regarding #2

The equipment and processes for aligned bonding of wafers that were developed intitially for wafer level capping of MEMs devices are an example of equipment and processes that are used by both by MEMS and for 3D integration.

DRIE etching is another example of a process and equipment set that are used by both MEMS and 3DIC.

Also, it seems that some of the metal deposition techniques, particulary plating, are used in both.

Eric

Regarding #3

Thanks for getting things rolling Eric.  Can anyone add to this? What about simulation and modeling tools - are there synergies there?

Hello everyone and happy Monday!

Here's another question for you - What 3D integration technologies are also needed for MEMS integrations? I look forward to hearing your perspectives...and feel free to surprise and amaze....

It seems that hermetic covers are needed for most MEMs structures therefore backside vias - after the cover is applied - are the norm if someone choses to use TSVs.

Regarding #6

hi Phil - thanks for the comment. Can you perhaps list some applications where this is especially relevant?
Thanks, Karen

Regarding #6

The VIAs can also be placed in the cap and then the hermetic capping is made as the last step. It depends on the overall design and application what is most favorable.

Regarding #4

Not being very familiar with details I know that the software companies traditionally dealing with MEMS simulation have already added specific modules more dedicated towards 3D integration.

Other then that I thin Eric pretty much covered it main processes/equipments used in both bonding, DRIE and plating are the main ones. Process modules used in both are for example TSV modules and various bonding modules originally developed for MEMS. 

Regarding #3 and #5

I think Eric has mentioned the notables of current high interest shared topics for both MEMS and 3D IC, but I think to add to that list, it is also worth noting that a number of other more traditional processes like thin film and other packaging techniques, as well as previously less utilized polymer technologies are also finding their way into the mix.

I think as we all benefit from learning from novel applications, many traditional semiconductor processes as well as techniques from other emerging technologies will be adapted to benefit the structural nature of both MEMS and 3D IC technologies.

Salah -

I think you're absolutely right. Sharing expertise across the industries helps everyone leverage and adapt these technologies for their purposes, which in turn opens up new application possibilities. That's the whole point of this forum. :-)

Regarding #2

As already mentioned by several participants, there are many process steps that are common place in MEMS manufacturing that are also key enabling manufacturing steps for TSV and 3D integration technologies. These include wafer bonding (both temporary and permanent, wafer thinning, back-side / front-side alignment steps, DRIE and a range of other deposition and etch steps. Many of these steps are common in CMOS fabs and often existing equipment can be used to realise TSV processing. However, several steps are completely alien to most CMOS fabs and require specific tooling of the type more typically found in MEMS fabs; including for example wafer bonding and DRIE. However, even for common CMOS steps such as PVD metallisation, the challenges associated with TSV fabrication are very different to conventional CMOS processing and cannot be met with conventional equipment.    

David

Additional comments on #2

I think that it is worth focussing a little more on the plasma etch and deposition steps as these fall within SPTS’s area of expertise. Lets start with DRIE, based upon the Bosch Process. This is a technology that is synonymous with MEMS and well established as a production process for  many if not the majority of MEMS devices. Today, Bosch based DRIE is already established as the principal  etch technology for fabricating TSV’s. It offers an unparalleled process window and allows fabrication of vias that could never be etched using conventional non-Bosch CMOS processes. Today, because of the pioneering work done by MEMS engineers the DRIE process can deliver just about any aspect ratio via at competitive cost. Rarely would this process restrict a designer’s ability to generate a particular via process flow. It can cope with almost anything that you could ever want for TSV, including high aspect ratio, smooth sidewall vias, large vias used in interposer type applications and achieve all of the above on 300mm wafers at unparalleled etch rates.  Despite the dominant position of Bosch based processes in fabrication of vertical via structures, there is also a place for non-Bosch processes. DRIE systems can also be used to fabricate unique positively tapered via structures or the type used in CMOS image sensor packaging (eg. in the Tessera MVP process). One should not overlook this, as this application area is the largest and most well established wafer level packaging process in production today and such technologies will find increasing deployment in other 3D-IC schemes.

David

Yet more on #2

Even though the DRIE steps are proven, available, and rarely a significant technical hurdle, there are other challenges that the TSV fab faces. I believe that it is the via fill processes that represent the greatest challenges. Firstly, let’s consider via isolation. In many processes flows this must be a low temperature process following CMOS fabrication so <450deg C of even lower < 200 deg C where wafers are already bonded (as is typical in CIS packaging schemes). Spray coat polymer dielectrics are well established for some applications. These are sometimes an excellent solution, but are limited WRT the via profiles (hence pitch) and AR. Depositing conformal dielectrics such as TEOS SiO2 or SiH4 based SiON or SiNx to generate high quality, stable films as via isolation at low temperature is an area where again the MEMS community can offer up far more experience than can be found in the world of CMOS. Using our experience gained in MEMS and compound semiconductor processing, SPTS has done a great deal of work to allow deposition of high quality dielectrics at temperatures below 200 deg C. This opens up a whole new process window for TSV fabrication and I think an area where a great deal more effort needs to be applied by the TSV community.

It is in the PVD steps however where I feel that real longer term challenges exist. Today ionized PVD can offer excellent results far beyond what could be achieved using conventional sputtering. Using iPVD, barrier and Cu seed layers can be routinely deposited in vertical DRIE vias . However, it is difficult to imagine that the capability of such techniques can be extended far beyond 10:1 aspect ratios. And given that the trend is to increasingly high aspect ratios. I feel that other techniques such as Cu MOCVD (MOCVD TiN is already fairly common place) or electrochemical processing are going to become increasingly important in years to come. Again, this is an area where in my opinion the industry needs to apply some additional effort as solutions are not currently adequate to meet future need.

David.

Regarding #4

There are a couple of challenges in 3D integration that might be addressed with MEMS modeling software or expertise.  Intrinsic material stress is inherent in many MEMS designs and also occurs in TSV designs in a couple of places:

- stress in the TSV and liner layers.  For example for via-last technology, the VIA is filled with a conductor that expands and contracts at a different rate than the surrounding bulk Silicon.  This can cause cracking and de-lamination in the TSV structure.

- stressed silicon technology, used to enhace transistor performance.  The presence of a TSV nearby will affect stress and therefore device performance.

MEMS modeling tools are already equiped to model and understand these types of phenomena and might be profitably used to model TSVs and surrounding devices.

Also MEMS process modeling software can be a useful way to model process technology that's new to the IC world but has been around for several years in MEMS (DRIE, wafer bonding, etc as mentioned above).  Process modeling tools like Coventor's SEMulator3D or competitors can model these as well as other standard MEMS and IC process steps and are a useful way to understand a process, and to communicate process details to others.

Regarding #14

David -

Thanks for such thorough responses - you've already addressed some follow on questions!  You've explained a bit from the etch and metallization perspectives which technologes are used in both MEMS and TSV, and how experience gained in MEMS fabrication can be leveraged in TSV for 3D.  Panelists -  can you expand a bit in that area from your various perspectives? Besides etch and metalization, where do MEMS and 3D IC processes differ? For example, regarding TSVs - what are the differences in the requirements of TSV for MEMS vs. the requirements for 3D ICs?

(one little housekeeping note, if you click "reply" at the bottom of the comment you're responding to, there will be  a link to the referenced comment #)

Regarding #15

Ken -

So in other words, using simulation tools, you can determine  the different potential issues using various types of fill without actually working from a prototype?  Can you compare, for example the benefits and downfalls of using tungsten vs. copper fill?

Regarding #16

Regarding how MEMS and 3DICs differ - MEMS have a mechanical aspect, hence the name micro electro mechanical systems, and the mechanical portion involves different size scales and materials.  However, for this discussion I think it it probably most useful to focus on how the common processes differ in their application to 3D integration depending on integrating ICs or MEMS and CMOS or just building MEMS.  (I hope the preceding sentences made sense, it has been a long day at Semicon Europe.)  For wafer bonding 3DIC requires a conductive bond for signal transmission while this is not always required for MEMS and MEMS often requires a degree of hermeticity for the bonds which is not normally required for 3DIC.  Also, if the MEMS bond has conductive vias the number of vias is often low where 3DIC may require a large number of vias.  This means that 3DIC will typically require smaller vias and therefore tighter alignment.

Regarding #17

Francoise -

I think that simulation could be valuable to help understand the trade-offs between choices of materials and geometry.  So for example, tungsten and copper have different thermal and mechanical properties and so the residual stress in the TSV would change depending on the choice of material.  Perhaps one would cause TSV pop-ups while the other would not.

Also the reliability and residual stress depends on TSV diameter, length and pitch, so a choice of materials and process that is known to work at a particular TSV size may stop working as length scales and pitches shrink.  Simulation with MEMS type FEM tools could help to predict and understand such problems.

Having said that - prototypes are always going to be necessary at some point! But it's my hope that modeling and simulation can reduce the expense and time involved in new process development.

Perhaps the other panelists have some insight on whether this might be useful?  Or has the industry already moved past these problems?

Just a final note at the end of the day here in Dresden to round off the points made earlier concerning the similarities between plasma etch and deposition steps in MEMS and TSV fabrication. There are other less obvious areas where common requirements exist. One interesting one is the fact that in many cases the TSV etch will terminate on a buried dielectric layer. It is essential to be able to stop the etch process at the SiO2 interface without resulting in lateral etching or notching at the base of the via. This is exactly the same issue as seen when MEMS devices such as inertial MEMS, pressure sensors FBAR etc are fabricated using DRIE technology. And the same solutions that were developed for MEMS (such as advanced endpoint detection and pulsed, low frequency wafer biasing) are just as applicable to TSV. Also, after dielectric isolation of the via, the dielectric must be etched from the base of the vias. At this point the effective aspect ratio of the vias is very higher, far larger than any CMOS SiO2 etch process can address effectively. Again, MEMS technology already deals with these issues by using dedicated deep dielectric etch process modules that can readily meet the requirements. Add to this the need to etch polymers and provide other novel Si etch process steps such as blanket Si etch processes for stress relief following backgrinding and it becomes clear that MEMS offers up many, many developed solutions to the TSV engineer.  In fact it is these MEMS based solutions, rather than conventional CMOS type processing, that are really enabling 3D integration.

David

Regarding # 5

I was thinking about this earlier today. As has been discussed, there are many common process and modelling technologies that are shared between MEMS and 3D-IC. In the early days of MEMS, pioneers were quick to adopt the process technologies that were used in IC manufacturing as the basic platform, developing the additional steps required such as DRIE and wafer bonding and adapting those that were not quite the right fit, like PECVD and PVD along the way. Today the technology is migrating back in the other direction as CMOS foundries and IDMs develop TSV. But there is one area that I think MEMS could still learn a great deal from those CMOS fabs working on 3D integration. That is in standardisation. Coming from a CMOS background has meant that many teams working on TSV development are focussed on establishing a common platform with key “building block” steps that can used for a variety of applications. Yes there are many, many TSV solutions, but far less complexity in process flow than exists for MEMS where, as Yole would say, “the MEMS law of one product, one process” is still the norm! From a supply chain perspective, such moves to standardisation are extremely helpful for equipment suppliers. They allow the focussed development of new process capabilities with acceptable ROI potential. As both MEMS and 3D-IC technologies become more complex (300mm system development, higher process integration requirements with equipment suppliers working together etc) the cost of development also soar, so standardisation will benefit the whole supply chain allow the on goig devlopment of innovative solutions. The CMOS world has faced up to this challenge and would not be able to develop the advances that they continually do without standardisation. So in summary I think this is two way street in terms of learning!

David

WOW - this is a great discussion - thank you everyone for your insights and thoughts. But all this noodling has gotten me to thinking this question:

Are there times when the “rules” of MEMS design differ for the “rules “ of 3D integration design? Are the "rules" important to differentiate for either/both?

Regarding #21

I think this question goes along the same lines as what David is talking about, which is how can the synergies between MEMS and 3D IC technologies be best leveraged to provide cost effective solutions for MEMS IC stacking? For example, can the same 300mm tool line for 3D TSVs be used for MEMS manufacturing or vice versa?

Regarding #22

When it comes to design rules and limitations I think for neither MEMS or 3D integration they have been fully established yet. This situation with not fully estalished design rules is for IC industry and the associated 3D stacking a bit unusual nowadays but for MEMS something that is still quite a common situation. As rules and standards do get more established they would be more or less the same between the two disciplines and set by the capabilities of the machines used. The difference would mainly be that for MEMS you would have a wider set of materials (Au) to work with at least as long as the stacking is done within the same fab facilities as the IC. 

Regarding #23

You can use the same tool line as long as you don't run in to conflicts regarding use of materials. Remember however that although 3D stacking uses typical "MEMS tools" such as DRIE, plating and bonding you would need additional tools to manufacture MEMS as opposed to "only" doing 3D stacking.

Regarding #21

I have to agree with David's comment regarding standarization being an opportunity for the MEMS to learn from the CMOS world.  I have been around long enough to have seen how much resistance there was in the CMOS world when market forces started driving CMOS towards standard processes ~25 years ago.  I think we are going through the same process with MEMS and this time and in the MEMS world could clearly benefit from the CMOS world in this area.  "Those who do not learn from history are doomed to repeat it" - George Santayana.

Eric

I agree with Magnus regarding using the same tool lines but with caution on materials.  Specialized equipment is never a quick or easy solution, especially at the beginning, so you need to make do with what you have.  There are enough similarities that at least tools can be recycled, similar to early MEMS and fabrication from borrowing on semi tools.  Eventually things need to be added to the tool belt, but for now we are doing what we can, MEMS has provided more physical/structural capabilities with its more specific tool sets that 3D is benefitting from.

Regarding standardization- while I think it is a great concept, MEMS still has a long way to go.  Kudos to those trying and pursuing these advances, but it is a steep battle and it seems like many MEMS processes have less underlying common denominators than when CMOS was trying to consolidate.  The intrinisic architectures of both technologies are very different lending to some of the difficulties found in MEMS.  With this said, that doesn't necessarily mean that some level and form of standardization can't be achieved- it becomes more an issue of semantics as to what standardization is and what is acceptable.

We could go on this topic for hours, but I think the important thing here is that we continue to try to push towards making "sensible" standardization out of noteworthy trends we see from collective efforts in these spaces.

We've talked alot about processes and now standards - but only touched on materials, so lets talk a bit about that.  What opportunities exist for materials manufacturers in both MEMS and 3D IC markets?

Regarding #28

To sell more Cu, soldermetals and gases? On a more serious note I think that a really good, low temperature, easy to use bondmaterial that knocks out the competing materials and is open to use for everyone would probably sell a lot. However, I am unsure if it will be material side or rather machine vendors that would benefit most here. Something that is easier to hermetically fill a hole with and providing great conductivity, no thermal mismatch to Si and so on would also be great. Such a material everybody would want but I have no real idea what it would be in dollars.

As this is the last day we have the panelists participating, I'd like to ask them two wrap up questions. The discussion will stay open for a few weeks if anyone else would like to add comments.

First of all, what can the 3D IC community learn from the MEMS community, and vice versa?

And second, when and why does it make sense for companies to be involved in both MEMS and 3D ICs?

Karen - anything else to add?

Hi everyone - thanks for the great discussion and thoughts that helped educate me and I am sure the audience!  I was especially heartened to hear the mention of standards - as MIG is leading an initiative (along with our colleagues/partners at NIST and SEMI) on MEMS testing standards. I encourage those who are not involved in this initiative, to contact me and let me know what your thoughts are and where you are using standards (with respect to testing) and for the OEMs out there - why, what, how and when are MEMS testing standards important to you?

Thanks again - take care and see many of you at MEMS Executive Congress (www.memscongress.com) in Scottsdale November 3-4.