In this article, published in the May/June 2010 issue of Chip Scale Review Magazine, Steve Lerner, CEO, Alchimer, proposes a "variation on theme" for TSV cost-of-ownership.
3D integration and More-than-Moore are popular topics in the semiconductor industry, with
high expectations for eventual wide use of 3D-IC technologies. But the pace and
scale of adoption is largely dependent on long-term cost of ownership (CoO).
This article presents an alternate perspective from those through-silicon-via (TSV)
consortia oriented around adaptation of front-end processing, examining all
aspects from design to factory-floor deployment. (full story)
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One of the wrong statements
One of the wrong statements in this article is to say :
"... Therefore, the infrastructure to process such an interconnect vehicle (TSV) can and should be radically different from CMOS infrastructure. ..."
That's not what the industry is looking for. We need that TSV will be part of the CMOS as we are making the inter-metal vias. TSV should be seen as a SuperVia, and smoothly becoming in the futureas a regular via.
3D-IC integration will then become fully and true Three Dimentional.
If we follow the recommendations of Steve Lerner, we are stuck in an SiP world ... where dimensions counts 2.5, not 3 !
Hi Kholdoun, I'm
Hi Kholdoun,
I'm resonding on behalf of Steve Lerner, CEO Alchimer, who emailed me this reply to your comment and asked me to post it:
Dear Kholdoun,
Please allow me to clarify the confusion surrounding my message. The quote is correct, although I am not advocating taking TSV out of the CMOS infrastructure, but rather turning the current CMOS infrastructure on it's head. Please realize that in the context of manufacturing, the infrastructure consists of the overall physical and organizational structure, which includes facilities, services, and with greatest financial impact, the depreciation of notoriously expensive tools. The dry deposition tools being used today in the present CMOS infrastructure are not only inadequate in providing best in class design rules, they are over the top in terms of allowable cost for fabricating the dumb wires called TSVs, regardless of whether you apply via middle at the IDMs or via last in the OSATs . We fully support SuperVias, but not SuperBloated CMOS processing infrastructure. Keep in touch, and we will soon show you how committed we are to CMOS by announcing similar solutions in Dual Damascene.
Best regards,
Steve Lerner