3D Stacking Methods for TSVs (concluded)

By Francoise von Trapp on Apr. 28, 2010 Site: 3D InCites (Public) Forum: 3D Processes Forum - # of views: 3047

 

This week’s panelists reported on the current status of 3D TSV stacking configurations, with a central focus on progress in the chip-to-wafer (aka die-to-wafer) advancements to address speed, accuracy and throughput issues.

Gilbert Lecarpentier, product manager for SET, aptly noted that while C2C has been successfully implemented for flip chip bonding for Infrared Focal Plane Arrays applications and enables a wide choice of bonding processes, it doesn’t allow for subsequent process steps at the wafer level. Datacon’s Hannes Kostner concurred, adding that C2C doesn’t transfer well to high volume for TSV stacking, and that W2W lacks the flexibility. Adding the bonding perspective, EV Groups’s Thorsten Mathias noted that the two most frequently used bonding process, Cu-Cu thermocompression or Cu-Sn transient liquid phase (TLP) bonding, are better suited to the gang bonding processes in development that have been demonstrated to result in increased throughput and are more cost effective than serial bonding approaches required for C2C bonding.

 

The question of the best method for die sticking in the first step of the die placement/gang process was raised, with one suggestion from participant Scott Pozder, suggesting an uncured no flow underfill material. Lecarpentier explained about a patterned polymer process that’s been successfully demonstrated by IMEC. Chris Sanders weighed in with Ziptronix’ DBI process that allows for bonding and interconnect simultaneously.

 

Kostner offered more detail using the organic tacking material reference by Pozder, and added explanation for an alternative methodology when use of an organic material is not possible, for example when stacking MEMS and ASICs chips, instead using an ultrasonic tacking method in the pick-and-place step, followed by Cu-Sn TLP for final bonding.

Mathias offered some insight on the different bonding methods and what applications each is most suited to. He also offered a detailed explanation for why, despite the lack of flexibility in applications it can be used for, W2W is still a very attractive stacking option for 3D. Specifically, he explains why the known-good-die (KDG) argument for C2C and C2W stacking is easier said than done because it requires physical testing of the die before stacking, which in and of itself can be damaging; that cleanliness is easier to maintain W2W stacking because of particle contamination due to dicing; and that individual wafer yield will be higher than 2D because each functional layer will have a reduced number of mask levels thereby reducing the manufacturing complexity.

As Lecarpentier notes in his conclusion, solutions exist for C2C, C2W and W2W configurations. IMEC, Leti, SEMATECH and various consortiums all have ongoing programs focused on further developing C2W and W2W methodologies. We can expect to hear more about them at upcoming industry conferences, specifically a presentation at the MEPTEC MEMS Symposium on the MEMS ASIC stacking process in the European DAVID project, and a presentation on Cu-Cu bonding at year’s IITC 2010.

 

Good morning panalists. Thank you for joining us for this week's discussion on 3D stacking methods for TSVs.  The overall topic of this discussion has also turned up in earlier discussions this month in our 3D WLP update and also last week's 3D MEMS update.  Clearly, stacking approaches are a very important piece of the 3D TSV process flow.  Elpida has come out saying they will begin commercialization of Cu TSV processes for several applications using C2C stacking processes.  However, although C2C is a mature technology, when used for TSV stacking, it's been said to be a more costly approach.  Why then, start with C2C when C2W is an available option?

 

For several decades, D2D bonding has been successfully performed for the Infrared Focal Plane Arrays application; two dice of different nature are bonded together using the Flip Chip Approach. The accuracy requirement for the assembly of 3D die stacking with TSV is converging with the accuracy requirements for the High End IR-FPA (Bumps down to 4 microns, pitch down to 8 microns).  Processes such as in-situ reflow or room temperature compression have been successfully used to perform the heterogeneous integration of the compound semiconductor array with the silicon read out circuitry, mostly using Indium Bumps. D2D stacking enables a wide choice of bonding processing, but do not allow subsequent process step at wafer level. Wafer level processing is important for cost saving, but it brings additional challenges and bonding process choices are reduced. D2W population may takes a long time, to optimize the time, bonding techniques enabling a two step approach with high speed placement of die followed by gang bonding are investigated.

 

Good morning!

At the moment many companies have an established infrastructure for C2C stacking. C2W stacking is a comparatively new technology, which is not yet widely adopted. However, in the long run we expect that C2W will see widespread adoption due to the following reasons.

As Gilbert pointed out C2W enables subsequent wafer level processing like thinning or bumping.  Furthermore, many bonding processes for TSV are based on metal ion diffusion like Cu-Cu thermocompression bonding or Cu-Sn transient liquid phase (TLP) bonding. While these processes can be successfully implemented on C2C the throughput/cost analysis leads towards C2W for high volume applications. The diffusion rate is proportional to the temperature, time and pressure during the bonding process. For C2W all the dies are bonded simultaneously, which allows to implement sophisticated (but rather lengthy) temperature profiles. Serial processing with C2C is more time consuming especially if many dies have to be bonded to the wafer. 

 

Good Afternoon,

from my (= pick and place equipment manufacturer) point of view ,the mainstream solution for 3D stacking will be C2W technology using fast pick and place in a first step and final bonding as batch process of a populated wafer as second step. D2D is not scalable enough for mass production, while W2W is not flexible enough (yield, same die sizes needed...).

Thinking about a 2-step C2W process some developments needed for pick and place equipment seem to be clear or already done, like:

1) 12" placement area (already available)

2) Accuracy which is limited to 10µm@3s for the above mentioned placement area has to be increased to 3µm@3s over 12".

3) A suitable tacking method has to be developed to keep the dies in place while transferring the populated wafer from pick and place equipment to the final bond equipment.  

I hope that during this discussion additional features which are needed to do C2W bonding in 2 steps are posted. This would help to cross check the actual development roadmap for pick and place equipment...

 

What a great start to this discussion!  A year ago, the greatest limitation D2W (or C2W) was solving the accuracy vs. placement/bonding speed conundrum. There were tools that could achieve high accuracies (SET's die bonder comes to mind) but didn't have the necessary speed to make the process cost effective, while the flip chip bonders that had the speed (Datacon's tool comes to mine) didn't have tha accuracy.  Gang bonding as a solution, was just being investigated and now, it appears to have become the solution.  Could you each explain how your companies have approached the issue of achieveing both speed and accuracy for D2W (C2W) stacking?

 

Regarding #4

Hannes, 

I agree with your input that a better stick method prior to bond is needed.  In the paper we have in the IITC 2008 proceedings we demonstrated a special uncured no flow under fill could adhere the die prior to bonding.  In addition the electrical connects were not affected and the strength of the die bonds was robust enough to enable post bond grinding of the die.  At the time I thought it was interesting to be able to grind die after bond and avoid thin die handling. Although the die bonded were 280 µm thick this was not a problem compared to handling 50 to 20 µm thick die. 

Best Regards,

Scott Pozder 

 

Die sticking prior to bonding using patterned polymer has been successfully demonstrated by IMEC. They have been able to bond at 1.75µm accuracy using a wafer bonder after placing die on wafer using a 0.5µm accuracy die/flip chip bonder for placement. After benchmarking several polymers requiring elevated temperature for the die to stick to the wafer, the selected polymer allowed placement at room temperature.  Alternative methods such as oxide (ZIPTRONIX) or Cu-Cu molecular bonding (LETI) are investigated as a die attachment method.

 

Regarding #7

Two thoughts come to mind reading this post. Is IMEC getting connections using the polymer? The Ziptronix patented low temperature bonding process is bonding at the molecular level.

With our patented DBI(R) technology we not only get high bond strength at very low temperatures but also get interconnect at die to wafer and wafer to wafer bonding. The metals that can be used with DBI(R) are not specific and simply need to planarize with the oxide. We have achieved pixel level pitch interconnect at both the die to wafer and wafer to wafer level and have bonded high CTE mismatched materials due to the low temperature nature of our technology.

 

Chris, I know that ZIPTRONIX process is creating a full bond at molecular level using oxide; thank you for your clarification. LETI is doing molecular bonding as well for Cu-Cu interconnect. In the experiment carried out by IMEC, the polymer is patterned to leave open the window where the interconnections will occur. It secures the die at placement step; the electrical interconnection happen at the collective bonding step and the polymer complete the mechanical bonding (see the attached presentation made at IMAPS Device Packaging 2010 in Scottsdale, AZ)

 

Regarding #9

Gilbert, in reviewing this presentation, I see that the IMEC demonstrator of the hybrid collective bonding was done on a 200mm wafer. Has it also been demonstrated on 300mm wafers?

Also, the process requires two seperate tools - the die bonder and the wafer bonder for the collective bond. Does the wafer transfer time affect the throughput?  

 

Regarding #3

Thorsten -

What determines whether a Cu-Cu thermocompression bond or  Cu-Sn transient liquid phase (TLP) is used for the final bond?

 

Regarding #10

The idea of seperating the attachment of the die and the final bond in two different tools is actually to develop a process enabling higher throughput. The bonding time is one of the major contributor to cycle time. Collective bond results in higher throughput. When it comes to production, automatic transfer of the wafer into the final bond chamber will have to be implemented. 

 

Regarding #11

Let’s take a look at the specific processes. Cu-Cu thermocompression bonding requires high force and high temperatures in the range of 400°C. TLP bonding typically happens at lower temperatures, which is important in case the device has a low thermal budget or in case of heterogeneous integration (stacking of dies with different materials). TLP is slightly more forgiving for thickness variations of the dies and has less demanding surface quality specs. However, Cu-Cu thermocompression bonding has a more comfortable process window.  From the interconnect point of view Cu-Cu thermocompression bonding has the advantage that the resulting metallurgy is very well understood, whereas the TLP metallurgies are comparatively new. Cu-Sn was successfully qualified by Scott Pozder for stacking with TSVs (2008 IITC paper mentioned above) and by Infineon for face-to-face stacking, but still the industry knowledge for Cu-Cu interconnects is significantly higher.

 

Regarding #6,#13

Like Scott and Thorsten mentioned above there is a very successful qualification using a special no flow underfill to tack the dies to the wafer-substrate in the pick and place tool. So for stacking one die on a wafer this is my personal favorite in combination with Cu-Sn TLP for final bonding (The complete process flow including reliability results is shown in Scotts publication). A next step should be to evaluate this process stacking multiple dies to find out if several final bonding steps are necessary or if a multi stack can be soldered (using TLP) at once.

If organic material is not allowed in the interface there is another interesting tacking method for MEMs on ASIC bonding done in the european project DAVID. In this process we used Au-Sn TLP for final bonding and ultrasonic tacking in the pick and place machine. Nice was, that we were able to generate the necessary vacuum in the MEMs package while final bonding in an EVG C2W bonder. 

Regarding #5:

We have started RnD projects to make the following features available for the 8800 Chameo diebonder: 

1) 12" placement area with automatic transport capability of 12" wafer-substrates (status: available).

2) Increase accuracy from 10µm@3s to 7µm@3s (status: available for 8" now we are working on 12", looks good that we reach the target soon)

3) Increase accuracy from 7µm@3s to 3µm@3s with a production speed of 3600 uph. (status: started, concept available).

Sorry Francoise that I don't go into technical details how we increased the accuracy, but this is Datacon core know how which I don't want to share.

 

 

 

Regarding #12

SInce the bonding step is the longer of the two, Is it necessary to do the die placement step imediately followed by the bond step concurrently, one wafer at a time? Or is it possible (does it even make sense) to complete step #1 on an allotment of wafers, and then do the bonding step?  

 

Regarding #13

Thorsten - Would a good example of when to use Cu-Cu vs. TLP then be memory stacks for the former, and MEMS/IC integration for the latter?  Or memory/logic? 

 

Regarding #11

Is there a paper describing in detail the Cu-Cu interconnect process? I remember we have done TCB process but only with the Cu-Sn pillar bump. Good point also to know is the reliability performance of Cu-Cu vs. Cu-Sn in a specified test vehicle.

 

 

Regarding #16

Yes, for applications with small vias or high TSV density Cu-Cu is more popular. TLP bonding usually is used for larger bond pads and pitch.

In terms of the stacking process: the majority of the W2W integration projects use Cu-Cu bonding, whereas for C2W Cu-Sn bonding is more common.  

 

Regarding #17

Hi Dennis,

the "Handbook of 3D integrations" by Garrou, Bowers, Ramm (eds.) has a lot of information about the Cu-Cu bonding process.

Also at the upcoming IITC conference there will be a presentation about the recent progress in Cu-Cu wafer bonding (Paper #12.2, “Recent Advances in Submicron Alignment 300 mm Copper-Copper Thermocompressive Face-to-Face Wafer-to-Wafer Bonding and Integrated Infrared, High-Speed FIB Metrology,” W.H. Teh et al, SEMATECH/EV Group/FEI Co.)

 

Panelists,

Most of the discussion so far has focused on C2W processes and advancements.  Is W2W being dismissed as too high cost due to yield issues, and lack of flexibility, or is their development work being done to address these limitations?  

 

Regarding #20

Not at all, W2W is very much alive. All the leading semiconductor research institutes have programs for W2W (e.g. SEMATECH 3D program http://www.evgroup.com/en/about/news/56019/). In fact even during the economic downturn of 2009 the investments in W2W stacking for 3D integration with TSVs have gone up as companies have accelerated their R&D programs. Let’s take a closer look at flexibility and yield. It is true W2W only makes sense for dies of the same size, which is a severe limitation and limits the range of applications. However, there are applications where the same die size is possible and here W2W is a good option. Yield is a very complex and controversial topic. Known good die (KGD) manufacturing has always been a key argument for C2W or C2C. However, in reality it is not that easy to implement this concept. KGD requires testing of dies prior to stacking. From the microscopic level testing is equivalent to touching (or even scratching) the surface and thereby potentially creating a defect. This is especially true for spontaneous fusion bonds. The holy grail of die stacking is room temperature metal bonding as this would give a huge throughput advantage. It will be difficult to test millions of pads per die and maintain a defect free surface. However, if testing is not feasible then there is no yield difference between C2W and W2W. Another point is that it is easier to maintain cleanliness (and minimize particles) on the wafer level rather than on the die level after dicing. Some general thoughts on yield (valid for C2W and W2W) From the device point of view the high bandwidth enabled by high density TSVs allows implementing failure tolerant device architectures. From the processing point of view one of the underlying promises of 3D is that the individual wafer yield will be higher than currently for 2D. The reason is that each functional layer will have a reduced number of mask levels thereby reducing the manufacturing complexity.  E.g. memory has less mask levels than CPUs, but currently on-chip memory has to go through all the mask levels required for logic. So the wafers with few mask steps (=”cheap” die) should have a very high yield. The risk of wasting an “expensive” die (=many mask levels) by stacking it to a defective “cheap” die is reduced. Also shrinking the die size should increase the individual wafer yield (assuming that the number of particles per wafer will be kept at the same level). So overall W2W is a very active area in 3D.

 

So ultimately, is it safe to say that C2C has got the ball rolling with commercialization to 3D TSV stacking, but it will ultimately be replaced by C2W in most applications, and W2W in those that don't require same-size die?  It seems like the field of choices for TSV processes are narrowing across the board to those that make the most technological and economic sense.

 

 

As this is the final day of the discussion, I'd like to invite the panelists to add any final comments, or address any issues that weren't covered.

 

Françoise,

Thank you for having initiated that discussion.

Stacking D2D, D2W or W2W using TSVs is definitely getting huge interest. Solutions exist for all three techniques. Additional effort is required and, referring to some of the answers, is being done to achieve higher throughput at C2W. SET, who is already producing bonders with submicron placement accuracy, is joining that effort.