Updates on Package on Package technologies (concluded)

By Francoise von Trapp on Mar. 22, 2010 Site: 3D InCites (Public) Forum: 3D Packaging Forum - # of views: 3394

 

This discussion on the latest developments in package-on-package (PoP) technologies focused entirely on Amkor's TMV PoP, thanks to the participation of Lee Smith.  Here's what he had to report:

At this point, TMV PoP is fully qualified within Amkor, IC alpha and end customers.  The company is targeting Q2 2010 for ramp readiness production, with multiple customers coming on in the second half of 2010.  A recent presentation of SMT application notes and board reliability data was shared at IMAPS Device Packaging Conference, 2010, providing a basis for TMV PoP stacking application notes that Amkor will release in April.

 With regard to 2nd-generation TMV POP, Smith noted that application and roadmaps address large package sizes with large high density processor die and fine pitch bottom and top interface BGA patterns.  There could b a slight overlap between applications for substrate based TMV POP and 3D fan-out wafer level packaging technologies, but Smith believes they will be limited to niche applications. 3D FOWLP will have a better chance of adoption if it is focused on new applications.

In answer to Bill Acito's question about PoP having a standard top package, Smith explained that the  current standard PoP configuration is Memory on Logic, but that emerging technologies will allow for system-in-package integration of different devices combination like RF + digital.

Finally, Smith talked about 3D as the 4^th wave of packaging technology that addresses both the system) and IC design requirements.  Suppliers who can provide these diverse, application specific packages cost affectively through technology platform management will be the winners.

 

In the past few years as PoP configurations reached volume production, we’ve seen improvements in configurations aimed at reducing package height, reducing warpage issues, and improved methods of interconnect. In  2008, STATS ChipPAC introduced the Fan-in PoP; in 2009 Amkor introduced the through mold via (TMV) PoP, and Tessera introduced µmPLR technolgy. 

What is the current status of these technologies?

 

Regarding #1

Amkor's through mold via (TMV) PoP technology is fully qualified within Amkor, IC alpha customer and end customer who will be doing the SMT stacking one pass reflow process (where place bottom TMV pkg on paste printed PWB along with the other components, flux dip the top pkg and place on TMV solder pads of bottom pkg - then reflowed as complete PWB assy).  Ramp readiness has been exercised for production ramp in Q2 of 2010.  Multiple customers projected for production in 2H of 2010.

 

Regarding #2

Lee,

Thanks for the update. At the IMAPS DPC, Amkor presented a paper on surface mount technology (SMT) validation for TMV POP. Can you share the motivation that inspired this extensive evaluation process? 

 

Raj -

As you're stepping in for Flynn on this discussion, I'm hoping you can update on the progress with STATS Chip PAC's FiPoP. What's the status of this PoP configuration?

 

Regarding #3
SMT application notes are a key requirement for the adoption of new package technologies as are data on the associated solder joint / board level reliability (BLR).  Amkor's IMAPS presentation was a continuation of work on the SMT and BLR data for TMV PoP which was first reported at SMTAI Oct, 2008 in a joint paper with Sony Ericsson, EPTC June, 2009 in a joint paper with ST Microelctronics and Nokia, then SMTAI Oct, 2009 in a joint paper with Celestica.   This years IMAPS presentation provides the basis for TMV PoP stacking application notes which Amkor will release in April.

 

Are there already plans for the next-generation TMV PoP?  Over on our 3D WLP discussion, Xavier Baraton talked about 3D eWLB as a high-density PoP. And Nicolas Sillon and Bioh Kim talked about using  through polymer via interconnects to take Fan-out WLP and eWLB into the third dimension. Would you consider these to be competitive technologies to TMV PoP?

 

Regarding #7

There may be some application overlap between substrate based TMV PoP and so called 2nd generation 3D fanout wafer level package (FOWLP) technologies.  I believe this overlap would be limited to niche applications with small package sizes and low IO density.  To be cost affective in FOWLP devices to be integrated must be designed with pad layouts to enable 1 layer redistribution.  The applications and roadmaps we see for 2nd generation PoP requirements where TMV PoP plays, have large packge sizes with large high density processor die and fine pitch bottom and top interface BGA patterns.  Current generation PoP designs are well outside of the sweet spot for FOWLP and this gap gets much greater for the high density designs TMV PoP will serve.
However, there a many applications where the PoP structure and business model can provide cost / performance benefits for system designers with challenging integration requirements.  2nd gen 3D FOWLP will see better chances of adoption and commercialization focusing on new applications vs competing with the current and emerging PoP technologies in my view.

 

Lee,

Do most PoP configurations include a "fixed" or "standard" top package (e.g. memory), or are there designs where a system has been broken out into two packages (that only work with each other). Based on your answer, do you see that trend changing in the future?

 

Regarding #9

Bill,
Yes the vast majority of PoP applications stack a top memory package (single or combo memory) on to a bottom logic (mobile processor) package.  The memory interface may be a JEDEC standard (21-C developed thru JC-63) or a customer specific interface typically driven by an OEM.

There are emerging applications where PoP is used to provide electrical performance or optimize multi-chip integration yields by pretesting a low yielding device subassy before stacking.  The supply chain has seen total cost of ownership benefits through the PoP business model, so OEMs, semiconductor suppliers and packaging technology providers are exploring new applications for PoP.

So the trend is to realize the benefits of package on package stacking toward so called system on a package integration covering other device combinations like RF + digital.

 

Regarding #8

Lee, 

Your explanation brings to mind the wealth of options being developed to address different needs in the semiconductor electronics industry. There seems to be two schools of thought on this. One group says we need to narrow the field and settle on a few in order to solve all the design/test/supply chain issues with manufacturing them in volume. The other sees the value in this diferentiation, and that there is a market for application-specific 3D package configurations and niche applications. I'd be interested in yours, and the rest of the panel's input on this.

 

Experts report that 3-D is the 4th wave of packaging technology. Through hole, SMT (leadframe) and area array (BGA, CSP) were characterized as previous waves and those technologies continue to see wide use in high volumes with diverse package offerings in each technology.  Now system and IC designers look for specific cost / performance requirements in packaging technologies. 3-D packaging sees even stronger application specific requirements as 3-D addresses both the system (function, PWB - SMT assy) and IC design (multi-chip + passives) requirements.  So application specific packaging to achieve cost / performance optimization considering system and semiconductor requirements is a given and suppliers that can provide these components cost affectively through technology platform management will be the winners.