Up until recently, the only available methodologies for performing necessary metallization steps for fabricating through-silicon vias (TSVs) relied on conventional dry processes like physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD). These processes each have weaknesses such as low throughput and high cost. In July 2009, Alchimer S.A. introduced a family of wet deposition processes for isolation, barrier, and copper seed layers for TSV metallization, which addresses such weaknesses, and is a cost-reduced alternative to conventional dry methods.
This concludes our inaugural Forum Discussion with our charter 3D sponsor, Alchimer. Any further questions regarding the topics here should be submitted to Kathy Cook.(kathy.cook@alchimer.com ). We look forward to more discussions with this team as the technology progresses.
In the meantime, if you're at IEEE 3D Systems Integration Conference next week, be sure to catch Alchimer's presentation "Wet-Process Deposition of TSV Liner and Metal Films", Tuesday, September 29, during the session titled "Other 3D IC Processes" from 3-4pm.
Welcome to a 3D InCites In-Depth Discussion, which will run here from Sept. 21 – 25. I'd like to introduce Alchimer’s executive team: Steve Lerner, CEO; Kathy Cook, Director of
Business Development; and Claudio Truzzi, CTO, and thank them for joining me in this week-long discussion focused on exposing these weaknesses and explaining how Alchimer’s processes address them.
Kathy, before we get into the questions,
Could you please
summarize, in 100 words or less,Alchimer’s core technology?
Alchimer's Electrografting (eG) technology is an electrochemical-based process that enables the metallization of high aspect ratio (18:1) TSVs for 3D Interconnect while cutting wafer processing costs by 65% compared to traditional dry processes (CVD and PVD).
A key cost-saving aspect of Electrografting is the ability to use industry-standard electroplating equipment. The substrate surface is exposed to chemical precursors of the desired film. Electrons from the biased surface serve as "bonding seeds" for the precursor molecules. The process initiates the growth of the film, which is "grafted" onto the surface by the formation of covalent bonds between the precursor and the surface.
Assuming we are giving CVD and PVD an equal footing in TSV process capability, which is a stretch for anything with greater than 5:1 aspect ratio, the cost penalties in decending order are:
-Depreciation
-Materials consumption
-Labor
-Overhead
with Depreciation and Materials accounting for the mjority.
These vacuum based dry processes are far more complicated and costly to run than wet processes, which in recent years have become much cleaner, more efficient and self contained than plating systems of 10 - 15 years ago.
I'll answer this one. Our electrografting technology was first introduced into the semiconductor industry for the dual damascene market, but the high aspect ratio TSV requirements in the 3D IC market are an even better entry point for our technology. The high costs of TSV manufacturing using PVD and CVD along with the demand for smaller and smaller via diameters gave us the perfect opportunity to bring a more cost-competitive solution to device manufacturers.
Francoise, this trend is mainly driven by reduction in Silicon real estate. Smaller vias reduce the area consumption impact of TSV bundles and, under certain conditions, actually improve signal integrity. Assumming a constant via depth, Silicon real estate savings grow exponentially with increasing aspect ratio. Put otherwise, a 4X improvement in aspect ratio allows a 16X increase in the number of TSVs per given area. Potential signal integrity issues due to slimmer vias are handled according to design best practice approaches, such as alternating ground and signal TSVs in a grid-like pattern.
So far, the gating item to smaller vias has been the steep price tag to be paid when adopting historical dry or wet solutions. Our technology takes the cost issue out of the way and considerably broadens the design space for 3D-IC designers.
Claudio -
Ok - so giiven that higher aspect ratio vias translate to smaller vias, and therefore the ability to increase the number of vias per area, what are the target applications? Are we talking about making circuit-level interconnects more feasible from a cost perspective?
Yes, the overall Cost of Ownership (CoO) for dry-process TSV wafers is still too high: around 245 USD/wafer (300-mm) in volume for 10:1 aspect-ratio and assuming new capex investment, according to Yole Developpement. By running our electrografted full stack in depreciated plating equipment, IDMs can already break the 200$ /wafer limit, all other process steps unchanged.
Target applications for High Aspect Ratio (HAR) TSVs are MEMS, memory, combined logic + memory for mobile applications.
I wish I was online enough to have quicker response time but to answer your
latest, here goes. Consumables costs are reduced in two ways using Alchimer's
electrografting technology:
1. Electrografting is a surface reaction whereby material is deposited, or
better, 'grown' on the immersed surface, be it horizontal or vertical. As a
result, films are not only highly uniform and conformal by nature, but deposited
only in the amounts required for a given film. Contrast that with PVD, where
one must continue to deposit enough material to reach the most difficult region
of a structure, resulting in tremendous amounts of wasted material just to
create a continuous film, which will most likely not be uniform. A non uniform barrier
or seed film will then create the possibility of incomplete fill which is a
reliability problem, which is a yield problem, and which is a cost that no one
wants to incur.
2. Given the high degree of conformality and uniformity relative to any
surface, electrografting eliminates another common by-product of directional
dry deposition called overburden. As mentioned earlier, in typical dry high
aspect ratio metallization processes, the top surface of the wafer is overburdened
with excess material in order to get enough required material to deposit onto all surfaces
inside the via. This overburden then needs to be removed, currently through
costly CMP. In fact, the problem is so severe that some people are suggesting
yet another operation, backgrinding, be added to remove the bulk of overburdened
copper before going to the finer and more expensive CMP. Isn't this what
nanotechnology was to rescue us from, carving desired structures out of a bulk blocks,
as opposed to elegantly building up by the molecule?
As far as the cleanliness piece, electrografting as described above is an
aqueous process using mildly acidic solutions, compatible with all wafer fabs.
Systems are closed loop with easy in-line monitors.
Thanks for the detailed explanation - it really gives a clear picture of the benefits, in my opinion. (and don't worry about the time lapse -we've got all week! This format is asyncronous on purpose. Feel free to pace yourself.)
Kathy -
Backing up a bit to the target markets. Besides dual damascene and 3D ICs, has Alchimer identified any other target markets that would benefit from the AquiVia processes and chemistries?
Understood. In that case, can you talk a bit about the customers you have in the TSV market? I know Dalsa was an early licensee for MEMS TSV applications.Can you share a bit about that relationship?
Dalsa has been a great supporter of our technology from an early stage. We have been working very closely with them for quite some time now, and I expect that we will continue to do so. The customers like Dalsa that recognize the advantages of our technology and don't allow their capabilities to be dictated by a few large equipment suppliers are the ones that will reap the rewards over the long haul.
Do you also have customers using Alchimer's technologies for applications other than MEMS? Claudio mentioned memory, and combined memory + logic for mobile application. Can you expand on that?
We are working with several tier one customers on applications that include mixed products, memory, image sensors and MEMS. Each customer is in a different stage of implementation, but they all recognize the value that our AquiVia technology brings to their products.
Hi Kathy, I can very well see the advantages of using wet processing, especially when it comes to more aggressive features where the traditional ways of applying these layers have limitations.
Can you please give me some insight into Alchimer’s Aquivia process, in particularly the insulator step? How the characteristics of this material are comparing with insulators currently used in the industry? Is your process applicable to any type of wafers?
Considering 3D Interconnect applications, are there any limitations with respect to feature dimensions/aspect ratios for application of your entire Aquivia process? Thank you.
The Aquivia insulator layer has properties similar to insulators produced by traditional methods. The chart below shows a few of those properties.Most of our work to date has been completed on p-doped wafers, but we have recently been doing work on n-doped substrates as well. Because the insulator layer is the only layer that makes contact with the substrate directly, most of the work that needs to be done for n-doped substrates is in the insulator layer. Nothing else should really change.
We really don't see any limitations as far as via dimensions and aspect ratios. We have certainly been able to produce any aspect ratio that has been requested of us so far, and that has been 18:1.
Given the nature of the DRIE and the fact that scallops are present, does aquivia allow for even depositioin of the sidewalls and if so what is the maximum sidewall scallop that this been demonstrated to date?
That is an excellent question. Electrografting can accommodate any scallop depth. Feasibility on 1um scallop depth has been done so far without any issues. Since scallop depth increases with etch rate, AquiVia allows our customers to drastically increase their etch rates. This further reduces the cost of ownership of our technology compared to traditional dry metallization.
I loath the idea of having to use TSVs of heights more than 10 microns because of the hard mask under cut problem. In some cases this under cut causes more issues than scallops in the TSV. Can Alchimer technology mitigate this issue or must this be solved by CVD or PVD film deposition. I like extreme thinning but this not always possible when bulk Si is used.
That's a great point and one that I think you'll find many of the etch equipment vendors now have solutions for. I know that it was a clear target that we at STS had at the beginning of this year and I pleased to say we can now achieve zero undercut with minimum scallop size although from Kathy's comments on AquiVia the scallop size should nolonger be a problem.
Given the fact that Electrografting layers are grown by the molecule from the surface up, as opposed to be deposited unto, they conformally grow on any topography, including severe undercuts, as shown i the following picture:
We believe that a cost competitive technology enabling high aspect-ratio TSVs is key to drive the overall 3D-IC CoO down, including thicker vs. thinner wafer handling.
Here is an image that demonstrates the insensitivity of AquiVia to an extremely scalloped via surface.
Note the scale at the bottom left of the image. These layers are completely conformal to the surface of the via. All three of the AquiVia layers are shown in this picture. The isolation layer is the dark inner-most layer immediately contacting the scalloped via surface. The middle layer is the barrier, and the outer-most layer is ViaCoat, our copper seed layer. As mentioned previously, this ability to provide conformal coverage is highly scalloped surfaces enables customers to increase their etch rates and thus lower their cost of ownership for their TSV processes.
It appears that traditionally, these processes are done using copper. However, I understand some companies are investigating other materials as well. Do AquiVia processes accomodate materials other than copper?
Currently AquiVia is only available for copper, but there is no technical reason that the same electrografting technology can't be applied to other metals. We'll keep you posted on new developments as new generations of AquiVia are released. I think you'll find that we will have some exciting announcements regarding this topic in the coming weeks.
We seem to have covered a lot of ground here this week. I know I have
a much better understanding of how the electrografting works (and I
hope our readers do to).
Although the greatest differentiator is the wet vs. dry approach to
deposition, I found the "growing" seed layer vs. depositing material to
be another critical difference that I hadn't fully understood before
this discussion. I can actually visualize the process much better now.
To wrap up, I'm wondering, although the AquiVia processes can be
performed on industry standard equipment, it is conceptually a great
diversion from conventional processes. What is the greatest challenge
you face in getting a rather conservative industry to switch over?
Thank you for hosting this discussion. It has generated some excellent discussions. One of our greatest challenges is letting the industry know that this technology is available so that customers don't have to let their design rules be dictated by limitations in traditional semiconductor equipment. And that's exactly what we plan to do -- starting with the 3DIC conference next week in San Francisco. We will also be at the IWLPC conference in October and the RTI conference in December. Anyone who doesn't know who we are and what benefits our AquiVia technology brings to the table by the end of this year will not have been paying attention.
You get right to the heart of the matter. The technical side is easy, as our processes
have been designed to work with low cost legacy equipment, and so the real task
at hand is to take the argument to levels where P&L and strategic positioning
matter most. Since we don’t have the bandwidth to lobby an entire industry that
has been beaten into conservatism, we are focusing on a few players that are
capable of assessing value and placing bets irrespective of pressure from the
incumbents. So short term, the objective is to gain traction with those
leaders, who in turn will start the snow ball. It's very much a global game of re-shuffling
the building blocks for a new paradigm, something that still allows for some fun
in a conservative industry. Speaking of fun, your show has been just that. Keep
up the good work, and all the best with Incites.
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Most of our work to date has been completed on p-doped wafers, but we have recently been doing work on n-doped substrates as well. Because the insulator layer is the only layer that makes contact with the substrate directly, most of the work that needs to be done for n-doped substrates is in the insulator layer. Nothing else should really change. 
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Francoise von TrappReaders and Participants -
This concludes our inaugural Forum Discussion with our charter 3D sponsor, Alchimer. Any further questions regarding the topics here should be submitted to Kathy Cook.(kathy.cook@alchimer.com ). We look forward to more discussions with this team as the technology progresses.
In the meantime, if you're at IEEE 3D Systems Integration Conference next week, be sure to catch Alchimer's presentation "Wet-Process Deposition of TSV Liner and Metal Films", Tuesday, September 29, during the session titled "Other 3D IC Processes" from 3-4pm.