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3D IC Technology Progress & Limitations

Developments in methodologies for 3D integration schemes using TSV interconnect have been moving forward at a good pace, however there are still areas to be addressed. This forum will address both the progress being made thus far, and the roadblocks yet to be addressed.

Moderator: Robert Petrossian,Francoise von Trapp

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3D IC's position along the technology curve By Francoise von Trapp on Jul. 06, 2009 - 8 replies		1780	07/26/2009 3:23pm

What problems does 3D solve? By Francoise von Trapp on Jul. 06, 2009 - 12 replies		1199	07/26/2009 4:07pm

If nine-die stacks can be done with wire bonding, why go to TSV? By Francoise von Trapp on Jul. 06, 2009 - 5 replies		2222	07/26/2009 4:17pm

What capabilities are required of EDA tools? By Francoise von Trapp on Jul. 09, 2009 - 9 replies		1694	07/26/2009 4:43pm

Will alternative methods of interconnect slow down TSV's progress? By Francoise von Trapp on Jul. 09, 2009 - 1 reply		1179	07/09/2009 12:57pm

How should 3D ICs be tested, and what difficulties does this present? By Francoise von Trapp on Jul. 09, 2009 - 4 replies		1543	07/26/2009 4:58pm

What simulation capabilities will be required to support 3D IC process development? By Francoise von Trapp on Jul. 09, 2009 - 2 replies		1202	07/09/2009 4:07pm

Is the pick-and-place tool speed/accuracy issue being addressed? By Francoise von Trapp on Jul. 20, 2009 - 1 reply		1475	07/22/2009 7:11pm

excillent By Atul Bajpai on May. 28, 2010 - 0 reply		1250	No replies yet

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